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  1. Supplementary files
  2. Semiconductor Interfaces at the Sub-Nanometer Scale
  3. Semiconductor Interfaces at the Sub-Nanometer Scale
  4. Semiconductor Interfaces at the Sub-Nanometer Scale | H.W.M Salemink | Springer

Specifically, the resistivity of metal interconnects and metal-semiconductor contacts increases due to downscaling.

The metal-semiconductor contact resistance is becoming a performance limiting factor as it takes larger fraction of the total on-state resistance [2]. Hence, the contact resistance must be reduced to meet ITRS performance requirements of future technology nodes. As metal-semiconductor interface shrinks simultaneously as device shrinks, it becomes questionable if the resistivity still can meet the ITRS requirements when it reaches to the certain scaling limit subnm.

This work investigates the effects of contact geometry, Schottky barrier height, and doping concentration on the specific contact resistivity. Published in: 71st Device Research Conference. Article :. DOI: Need Help? The reason is that the strain energy in a material increases as its thickness increases; in contrast to the bulk, at the same stress, a thin sheet will not contain sufficient strain energy to create dislocations or does not contain sufficient strain energy to fracture[ 42 ]. It is thus possible to make new strained materials using crystal symmetry as the driver[ 28 ].

Tensilely strained Si has emerged as an option for complementary metal oxide semiconductor devices because of its high carrier mobility[ 36 , 43 ]. Traditional methods to fabricate tensilely strained Si rely on epitaxial growth of a Si layer on plastically relaxed SiGe substrates.

This process does produce strained Si , although with nonuniform strain and with roughness. It is not effective, however, for fabricating strained Si For a given Ge concentration, the kinetic critical thickness for plastic relaxation is much lower in the than in the orientation.